#---------------------------------------------------------------------- 
# NOTE : This file is automatically maintained and could be
#        regenerated at any time. 
#
#        DO NOT CHANGE THIS FILE except in the ways sugested in
#        the comments.
#---------------------------------------------------------------------- 

# The MODULE variable should be set to the name of the module.
# Module names must be unique across the entire project.

MODULE = test_001

# The initial.mak makefile fragment contains variable definitions
# that must be included before the other standard makefile fragments
# are included.

include ${PROJ_MAKEFILES}/initial.mak


# The generation.mak makefile fragment contains targets required to
# generate (or perhaps regenerate) a modules Makefile from the
# project Makefile template.

include ${PROJ_MAKEFILES}/generation.mak

# The traversal.mak makefile fragment contains targets required to
# traverse a directory hierarchy.  It requires the LocalDepends.mak
# makefile fragment to define the list of submodules.

include ${PROJ_MAKEFILES}/traversal.mak


# If you require a module-specific makefile fragment to be included
# before all the other standard makefile fragments, then use the
# command "make Makefile.prepend" to generate a new
# Makefile.prepend file, and then uncomment the following
# include line.

# include Makefile.prepend

# ------------------------------------------------------------
# add the names of local source files in this directory to this
# variable.

LOCAL_SOURCE_FILES =  

SVN_FILES += ${LOCAL_SOURCE_FILES}

# add the names of any subdirectories in this directory to this
# variable

SUBMODULES =  


# ------------------------------------------------------------
# customisatin appears here.

# If you wish to use xilinx ise uncomment the following line.
# include ${PROJ_MAKEFILES}/xilinx_ise.mak

#
# Verilog
#

# add directories containing modules instantiated in this modules
# here.
VERILOG_MODULE_DIRS    = ../modules/dcom_apb .

# add library directories used by this module here.
VERILOG_LIBRARY_DIRS   =

# add specific library files here (i.e. precompiled or single files
# containing multiple module definitions).
VERILOG_LIBRARY_FILES  =

# add directories containing letlist verilog for netlist simms here.
VERILOG_NETLIST_DIRS   =

# add directiries that point to black box instances of modules if
# required.
VERILOG_BLACK_BOX_DIRS =

# if you wish to use Hatch register generation uncomment the following
# line, it needs to be before any verilog makefile fragment :
include ${PROJ_MAKEFILES}/hatch.mak

# If you wish to simuilate a testbench using iverilog uncomment the
# following line:
include ${PROJ_MAKEFILES}/iverilog.mak

# ------------------------------------------------------------

# If you require a module-specific makefile fragment to be included
# after all the other standard makefile fragments, then use the
# command "make Makefile.postpend" to generate a new
# Makefile.postpend file, and then uncomment the following
# include line.

# include Makefile.postpend

# The final.mak makefile fragment contains targets that must be
# included after the other standard lego makefile fragments are
# included.

include ${PROJ_MAKEFILES}/final.mak

#---------------------------------------------------------------------
# Local Variables:
# mode: makefile
# End:
# End of Makefile
